A typical titanium silicide process consists of four steps: titanium deposition, a silicide react step, a TiN (titanium nitride) strip, and a silicide anneal. During the react step, titanium is reacted in a N.sub.2 (nitrogen) ambient to fore titanium-silicide where the titanium reacts with silicon, and TiN is formed elsewhere. The silicide formed during the react step is typically present in a higher resistivity phase known as C49. TiN strip step removes the TiN layer formed during the react step. The anneal step is then used to transform the high resistivity C49 silicide phase into a lower resistivity silicide phase known as C54.
Silicide cladding of the polysilicon gate and the source/drain regions in VLSI (very large scale integrated) circuits using titanium silicide is a popular approach for reducing the transistor series resistance and local interconnect delays in VLSI circuits. The sheet resistance of heavily doped, silicided polysilicon lines is known to be a function of linewidth, particularly for sub-micron linewidths. One explanation for this is that a lower percentage of the silicide transforms from the higher resistivity C49 phase to the lower resistivity C54 phase on sub-0.5 .mu.m polysilicon lines. Another explanation is non-uniform silicide formation. Sheet resistances for linewidths under 0.5 .mu.m are particularly problematic. Hence, there is a need to alleviate this problem and reduce the dependence of the silicide sheet resistance on linewidth.
Several methods have been used to reduce the titanium-silicide sheet resistance. One method of reducing the silicide sheet resistance is to increase the temperature of the anneal. However, higher temperature leads to agglomeration of the silicide. Higher temperature also leads to lateral overgrowth of the silicide which is unacceptable for self-aligned silicide processing. Lateral overgrowth results in undesirable conductive silicide stringers between the polysilicon gate and the source/drain region of MOS transistors. Therefore, an alternative method is desirable for reducing silicide sheet resistance.
A method that has been used in conjunction with cobalt-silicide includes a titanium nitride capping layer. The titanium-nitride capping layer is used during the silicide react step to reduce cobalt overgrowth on oxide areas and reduce the variability of the sheet resistance. The titanium nitride capping layer reduces oxygen contaminants in the cobalt silicide. By reducing the contaminants in the forming silicide layer, the sheet resistance of the cobalt silicide is reduced.